发明名称 Pipeline signal processor
摘要 A signal processor including a programmable arithmetic controller and a pipeline arithmetic unit controlled by such controller is disclosed. The arithmetic unit includes a plurality of serially coupled processing levels. The arithmetic controller includes a corresponding plurality of serially coupled control levels, each one of such control levels being coupled to a corresponding one of the processing levels. Each one of the processing levels passes digital data applied thereto in accordance with a control instruction applied to such processing level by the arithmetic controller. As data passes through the various processing levels, the control instruction associated with such data passes through the corresponding control level so that such control instruction "follows" such data as both data and control instruction pass through the processor. In this way the processor is adapted to start a new process concurrently as such processor completes a prior process.
申请公布号 US3875391(A) 申请公布日期 1975.04.01
申请号 US19730412070 申请日期 1973.11.02
申请人 RAYTHEON COMPANY 发明人 SHAPIRO, GERALD N.;SOBEL, HERBERT S.
分类号 G05B19/414;G06F9/38;G06F17/10;(IPC1-7):G06F7/38;G06F15/00 主分类号 G05B19/414
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