| 摘要 |
A semi-custom semiconductor device adapted for a master slice approach includes basic cells arranged in an array, wherein the cells are configured such that connection hole placeable positions are at lattice points of a grid which is spaced a predetermined distance from a custom wiring grid having a uniform predetermined lattice spacing. The semiconductor device is prepared by forming basic cells in a silicon wafer as an array, forming a first interlayer insulating film thereon, perforating contact holes at all contact hole placeable positions aligned with lattice points of a grid spaced a predetermined distance from a customizing wiring grid through a contact hole sharing mask, forming a first metal layer thereon, thereby providing a master wafer, etching the master wafer through a custom mask to form a first metal wiring layer on the custom wiring grid and between it and the contact hole, forming a second interlayer insulating film-thereon, perforating via holes at via hole placeable positions aligned with lattice points of a grid spaced a predetermined distance from the customizing wiring grid, forming a second metal layer thereon, and etching the second metal layer to form a second metal wiring layer. The invention facilitates designing, reduces the development cost, and advances the delivery date of a semi-custom semiconductor device.
|
