发明名称 INTER-CIRCUIT BLOCK INTERFACE DEVICE
摘要 PURPOSE: To speed up the processing of a control signal from a CPU to perform the input/output control, the storage/readout in/from buffer memory and distribution/concentration to plural input/output circuits, etc., of an ATM multiplex signal. CONSTITUTION: An interface 9 in which an entry sequence output memory device is arranged is provided between a central processing control unit 8 and a control circuit 6, and the control signal of the central processing control unit 8 is stored transiently in the entry sequence output memory device, and the control signal stored in the entry sequence output memory device is sent out to the control circuit 6 corresponding to the processing speed of the control circuit 6.
申请公布号 JPH08331122(A) 申请公布日期 1996.12.13
申请号 JP19950155172 申请日期 1995.05.30
申请人 TOKYO DENSHI SEKKEI KK 发明人 SHIMURA MASARU
分类号 H04Q3/00;H04L12/02;H04L12/28;(IPC1-7):H04L12/02 主分类号 H04Q3/00
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