Column redundancy circuit for semiconductor memory

摘要

The present invention relates to a column redundancy circuit for a semiconductor memory which can facilitate a high integration semiconductor circuit whose memory array is divided into a plurality of array units to be properly operated at a high frequency. The plurality of array units in the memory array include a plurality of normal memory cells and a plurality of redundancy memory cells. The normal data stored in the plurality of normal memory cells and the redundancy data stored in the plurality of redundancy memory cells are outputted through a local normal input/output line and a local redundancy input/output line, respectively. The column redundancy unit outputs a redundancy enable signal according to a column address, a row address, and a state of a fuse. The normal data stored in the plurality of normal memory cells or the redundancy data stored in the plurality of redundancy memory cells is selected according to a logical state of the redundancy enable signal, and outputted to a main amplifier via a global input/output line.