MEMORY SYSTEM

摘要

PROBLEM TO BE SOLVED: To avoid trouble due to a hardware fault which fixes a memory cell having a defect in a high-resistance state or a low resistance state. SOLUTION: This memory system 20 comprises: a memory cell array 28; a write circuit 30 structured so as to write the memory cells 32 in the array 28; and a control circuit 24 structured so as to control the write circuit 30 to receive data to supply the coded received data 130 coincident with fault patterns 110 and 132 of the array 28 and to write the encoded received data 130 in fault addresses 108 of the fault patterns 110 and 132 of the array 28. COPYRIGHT: (C)2005,JPO&NCIPI