发明名称 |
Sizing power-gated sections by constraining voltage droop |
摘要 |
A method for powering up a circuit comprising a plurality of sections of progressively increasing size is described. The method comprises receiving a signal for powering up the circuit, and, in response to the signal, sequentially powering up the plurality of sections in an order of increasing size. |
申请公布号 |
US9367054(B2) |
申请公布日期 |
2016.06.14 |
申请号 |
US201414157503 |
申请日期 |
2014.01.16 |
申请人 |
QUALCOMM Incorporated |
发明人 |
Coutts Ryan Michael |
分类号 |
G05B13/02;H03K17/687;G01R27/26;G01R21/00;G01R19/00;H03K19/00;H03K19/003;G05F1/56 |
主分类号 |
G05B13/02 |
代理机构 |
Loza & Loza LLP |
代理人 |
Loza & Loza LLP |
主权项 |
1. A method for sizing power-gated sections in a downstream circuit, the method comprising:
determining a capacitance for a first section based on a capacitance of an upstream circuit, and a voltage-droop constraint; determining a capacitance for a second section based on the capacitance of the upstream circuit, the voltage-droop constraint, and the determined capacitance for the first section; determining a capacitance for a third section based on the capacitance of the upstream circuit, the voltage-droop constraint, and the determined capacitances for the first and second sections; and determining a size for each of the first, second and third sections based on the determined capacitance for each of the sections. |
地址 |
San Diego CA US |