发明名称 MONOLITHIC INTEGRATED CIRCUIT AND MANUFACTURE THEREOF
摘要 PURPOSE:To reduce stress to be applied according to the insulating film of an FET, and to manufacture a monolithic integrated circuit having a low noise factor by a method wherein film thickness of the insulating film on the active region of the field effect transistor is made smaller than film thickness of an insulating film interposed between an upper layer metal line and a lower layer metal line. CONSTITUTION:The parts of a CVD SiO2 film 1 directly under upper layer metal lines 105, 115 are film thickness of the CVD SiO2 film 1a the same with film thickness of 3,000-6,000Angstrom of the usual CVD SiO2 film 104, while the CVD SiO2 film 1b at the part having no upper layer metal line, namely at the respective regions of the source and the gate of an FET is thin, and formed to 2,000Angstrom or less.
申请公布号 JPS60260156(A) 申请公布日期 1985.12.23
申请号 JP19840114656 申请日期 1984.06.06
申请人 TOSHIBA KK 发明人 ODA YUUJI
分类号 H01L29/812;H01L21/338;H01L21/822;H01L27/04;H01L27/06 主分类号 H01L29/812
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