| 摘要 |
An improved high speed bus and protocol are disclosed that are capable of transferring data in multiple modes. The bus is particularly useful in computer systems that require data transfer between a variety of computer peripheral memory devices. In base transfer mode, the bus is capable of a maximum of 32-bit data transfers while in extended transfer mode, the bus is capable of a maximum of 64-bit data transfers. The bus comprises a plurality of lines including address lines, size lines, data lines and various control lines. In its extended transfer mode, the bus is capable of employing a number of address and control lines as data transfer lines. The bus is also capable of disabling a device when the device is accessed in a transfer mode that the device does not support.
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