发明名称 Parallel counter and a logic circuit for performing multiplication
摘要 A logic circuit such as a parallel counter comprises logic for generating output bits as elementary symmetric functions of the input bits. The parallel counter can be used in a multiplication circuit. A multiplication circuit is also provided in which an array of combinations of each bit of a binary number with each other bit of another binary number is generated having a reduced form in order to reduce the steps required in array reduction.
申请公布号 US2002078110(A1) 申请公布日期 2002.06.20
申请号 US20010917257 申请日期 2001.07.27
申请人 RUMYNIN DMITRIY;TALWAR SUNIL;MEULEMANS PETER 发明人 RUMYNIN DMITRIY;TALWAR SUNIL;MEULEMANS PETER
分类号 G06F7/52;G06F7/60;(IPC1-7):G06F7/00 主分类号 G06F7/52
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