SENSE AMPLIFIER DRIVING CIRCUIT OF BIT LINE

摘要

A bit line sense-amplifier driving circuit controls a sense-amplifier of a cell array block, minimizes a voltage drop of a power line, and increases an operation speed of the bit line sense-amplifier. The bit line sense-amplifier driving circuit includes: first and second PMOS transistors serially connected between a power-supply potential and a pull-up sense-amplifier driving signal(rto); and first and second NMOS transistors serially connected between a ground potential and a pull-down sense-amplifier driving signal(/s). The first PMOS transistor and the first NMOS transistor are enabled by a first sense signal. The second PMOS transistor and the second NMOS transistor are enabled by a combination between a second sense signal and a column address signal. The second sense signal is deplayed by a constant time. The column address signal passes through a column predecoder, and is inverted and not inverted.