发明名称 |
PARALLEL PROCESSOR WITH REDUNDANCY OF PROCESSOR PAIRS |
摘要 |
General purpose parallel computer, latency reduction MIMD, with multiple processors and multiple memory address spaces, wherein processors (SPU) are redundantly replicated on each memory (M) bus (C-BUS) and, formed/connected as either master-active or slave-inactive of the bus and to interface a suitable communication structure (A-S) for transferring among themselves the process context and the bus control, in such a way to execute in turn a unique migrant sequential process per bus (C-BUS), and wherein each processor is also directly and tightly coupled with devoted private buses (P-P) to one corresponding processor of another one bus (C-BUS) in a way to form, between distinct buses (C-BUS), biprocessor pairs (DPU) capable of allowing communication and synchronization of the parallel migrant processes.
|
申请公布号 |
WO9745795(A1) |
申请公布日期 |
1997.12.04 |
申请号 |
WO1997IT00121 |
申请日期 |
1997.05.28 |
申请人 |
ESPOSITO, ANTONIO;ESPOSITO, ROSARIO |
发明人 |
ESPOSITO, ANTONIO;ESPOSITO, ROSARIO |
分类号 |
G06F15/16;G06F11/20;G06F15/80;(IPC1-7):G06F15/80 |
主分类号 |
G06F15/16 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|