| 摘要 |
<p>In a process for quickly determining whether there is a cache hit in cache memory systems utilizing error corrected tags, the hit detection process is split into two paths: the first path includes a circuit to check and correct a tag stored in the cache memory and the second path tests the validity of the tag stored in the cache memory by computing the appropriate ECC information using memory address information supplied by the computer CPU and comprising the tag and ECC stored in the cache memory with the CPU address and computed ECC. As the computed ECC is performed in parallel with the cache RAM access, this second path provides hit confirmation faster than the first path which must process the tag and ECC stored in the cache RAM through a ECC check and correction circuit. If a fast hit is confirmed, then the cache memory system can proceed to supply cache data to the CPU. If a fast hit is not confirmed, then the cache memory system waits for the first path to check and correct, if required, the tag stored in the cache and then test the corrected tag. <IMAGE></p> |
