| 摘要 |
<p>PROBLEM TO BE SOLVED: To prevent the leak of data transferred between a CPU and a memory through a data bus to the outside. SOLUTION: The CPU and the memory are connected together through an address bus 13, the data bus 14, a read signal wire 15 and a write signal wire 16. A read control signal and a write control signal transferred through the read signal wire 15 and the write signal wire 16 are provided to a control signal generation circuit 18. The control signal generation circuit 18 detects the change of the read control signal and the write control signal transmitted to the read signal wire 15 and the write signal wire 15 and generates a control signal. The control signal generated by the control signal generation circuit 18 is provided to a pseudo data generation circuit 19. The pseudo data generation circuit 19 generates pseudo data comprising unspecified random number data in response to the control signal and outputs the pseudo data on the data bus 14.</p> |
