| 发明名称 |
Method and apparatus for modulating and demodulating data into a variable length code and a providing medium for implementing the method |
| 摘要 |
A SYNC bit inserting section 14 adds a sync signal to a train of codes, after adding a minimum run, said sync signal having a pattern that breaks a maximum run. It is thereby possible to provide a reliable sync signal pattern.
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| 申请公布号 |
US2005168355(A1) |
申请公布日期 |
2005.08.04 |
| 申请号 |
US20050088464 |
申请日期 |
2005.03.24 |
| 申请人 |
|
发明人 |
NAKAGAWA TOSHIYUKI;SHIMPUKU YOSHIHIDE;NARAHARA TATSUYA |
| 分类号 |
H03M7/14;G11B20/14;H03M5/14;H04L7/00;H04L7/04;(IPC1-7):H03M7/00;H03M7/40 |
主分类号 |
H03M7/14 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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