Memory access control

摘要

Memory access circuitry controls access to multiple memory units with two access units. Arbitration circuitry forwards memory access requests for one memory unit to a first access unit, for a further memory unit to a second access unit, and for yet further memory unit to one of the first or second access units. The access units store requests in a queue prior to transmitting them to the respective memory unit. Tracking circuitry tracks requests and determines when to transmit subsequent requests from the queue. Control circuitry sets a state of each access unit to one of active, prepare and dormant, switches states of the two access units periodically, and does not set more than one access unit to the active state at the same time.

主权项

1. Memory access circuitry for controlling access to a memory comprising multiple memory units arranged in parallel with each other, said memory access circuitry comprising:
two access units each configured to select one of said multiple memory units in response to a received memory access request and to control and track subsequent accesses to said selected memory unit, said multiple memory units comprising at least three memory units; arbitration circuitry configured to receive said memory access requests from a system and to select and forward said memory access requests to one of said two access units, said arbitration circuitry being configured to forward a plurality of memory access requests for accessing one memory unit to a first of said two access units, and to forward a plurality of memory access requests for accessing a further memory unit to a second of said two access units and to subsequently forward a plurality of memory access requests for accessing a yet further memory unit to one of said first or second access units; said two access units comprising:
storing circuitry to store requests in a queue prior to transmitting said requests to said respective memory unit; andtracking circuitry to track said requests sent to said respective memory units and to determine when to transmit subsequent requests from said queue; and control circuitry configured to set a state of each of said two access units, said state being one of active, prepare and dormant, said access unit in said active state being operable to transmit both access and activate requests to said respective memory unit, said activate request preparing said access in said respective memory unit and said access request accessing said data, said access unit in said prepare state being operable to transmit said activate requests and not said access requests, said access unit in said dormant state being operable not to transmit either said access or said activate requests, said control circuitry being configured to switch states of said two access units periodically and to set not more than one of said access units to said active state at a same time.