Approach to predictive verification of write integrity in a memory driver

摘要

A subsystem is configured to apply an offset voltage to a test, or canary, SRAM write driver circuit to create a condition that induces failure of the write operation. The offset voltage is incrementally increased until failure of the test write operation occurs in the canary SRAM circuit. The subsystem then calculates a probability of failure for the actual, non-test SRAM write operation, which is performed by an equivalent driver circuit with zero offset. The subsystem then compares the result to a benchmark acceptable probability figure. If the calculated probability of failure is greater than the benchmark acceptable probability figure, corrective action is initiated. In this manner, actual failures of SRAM write operations are anticipated, and corrective action reduces their occurrence and their impact on system performance.

主权项

1. A computer-implemented method for predicting failures in a plurality of memory cells, the method comprising:
performing a first write operation to write first data to a first memory cell; determining that the first write operation has failed; in response to determining that the first write operation has failed, computing a first failure probability associated with a second memory cell based on a first voltage offset; determining that the first failure probability exceeds a threshold value; and applying a corrective action to the second memory cell.