发明名称 AUTOMATIC PHASING CIRCUIT AND DATA COMMUNICATION SYSTEM
摘要 PROBLEM TO BE SOLVED: To provide an automatic phasing circuit which selects a clock in the optimum phase with respect to data and a data communication system which surely performs phasing regardless of data. SOLUTION: The automatic phasing circuit is provided with a clock(CK) phase converting section which generates a second CK by dividing the frequency of a first CK having a frequency which is n times as high as that of input data(D) into 1/n divided frequencies and converts the second CK into n pieces of CKs having equal phase differences, a D phase converting section which converts the input D into n pieces of Ds having equal phase differences, and a coincidence/noncoincidence detecting section which compares the logical levels of the n pieces of Ds with each other. The phasing circuit is also provided with a section code generating section which generates a code used for selecting one CK from among the n pieces of Ds, a CK phase selecting section which selects one CK based on the outputs of the coincidence/noncoincidence detecting section, selection code generating section, and CK phase converting section, and a defined signal generating section which generates a defined signal indicating that the CK phase selecting section has selected one CK.
申请公布号 JP2002208916(A) 申请公布日期 2002.07.26
申请号 JP20010004240 申请日期 2001.01.11
申请人 FUJITSU LTD 发明人 KADOTA HIROTOMO;OYAMA KENICHI;SHIRAKAWA TAKAHIRO
分类号 H04L7/02 主分类号 H04L7/02
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