发明名称 |
Vector multiplier having parallel carry save adder trees |
摘要 |
High and low order bit carry propagation adders are connected to outputs of carry save adder trees which produce half-sums and half-carries. Following carry propagation addition of the low order bits carry propagation addition of the high order bits is carried out. A carry from the low order bit carry propagation addition is added to the high order bit carry propagation addtion.
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申请公布号 |
US4799183(A) |
申请公布日期 |
1989.01.17 |
申请号 |
US19860920600 |
申请日期 |
1986.10.20 |
申请人 |
HITACHI LTD. |
发明人 |
NAKANO, HIRAKU;MURAYAMA, HIROSHI |
分类号 |
G06F7/53;G06F7/506;G06F7/52;(IPC1-7):G06F7/52 |
主分类号 |
G06F7/53 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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