| 摘要 |
PURPOSE:To provide the phase locked loop(PLL) circuit with high accuracy and high speed locking. CONSTITUTION:In the PLL circuit comprising a phase comparator 1, an adaptive filter 2, two voltage controlled oscillators(VCOs) 3, 4 whose conversion gain differs from each other, a 1/N frequency divider 6, and a reference signal oscillator 7 or the like, the VCO 3 with a smaller conversion gain is selected up to synchronization locking and a timer 8 is used to throw a changeover switch 5 to select the VCO having a larger conversion gain after the end of synchronization locking after lapse of a prescribed time thereby attaining high speed locking and high accuracy for the PLL circuit. |
