发明名称 FRAME SYNCHRONIZING CIRCUIT
摘要 <p>PURPOSE:To minimize the hardware scale by sharing a memory for multiple point supervision with the delaying element of a strip control. CONSTITUTION:At the time of a pull out condition, in order to detect the frame pattern of an (n) point to exist for a frame bit period ((m)bit), input data are written to the (n) point same address of a memory 2 for an (m)bit, an (n) number of read data is compared with a frame pattern and a pattern detecting circuit 4 and the synchronization return is executed. However, at the time of the synchronizing condition, it is not necessary to compare the (n) number of data once, one bit of input data may be supervised for an (m)bit and therefore, the memory 2 is not necessary. Then, at the time of the synchronizing condition, the period of the wiring reading addresses of the memory 2 is controlled by a selecting circuit 6 so as to become from the (m)bit to a fixed delaying quantity lbit and the memory 2 is used as the delaying element of a strip control.</p>
申请公布号 JPH01258515(A) 申请公布日期 1989.10.16
申请号 JP19880085062 申请日期 1988.04.08
申请人 HITACHI LTD 发明人 SAKAI KAZUTAKA;ASHI MASAHIRO
分类号 H04J3/06;H04L7/08 主分类号 H04J3/06
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