发明名称 DATA DELAY CIRCUIT
摘要 PURPOSE:To attain data delay without dispersion or fluctuation by using a charge/discharge capacitor connected to an emitter follower circuit so as to select a discharge emitter follower for each inverting period of an input signal thereby shaping a discharge waveform. CONSTITUTION:When a signal at an input terminal 1 rises and a signal at an input terminal 2 falls at a time T1, the level of the emitter of a 1st transistor(TR) 1 is increased by an amplitude V, a 2nd TR 2 is turned off and an emitter of the TR 2 is increased by the amplitude V by a capacitor C1. Then the emitter potential is linearly decreased by the discharge of the capacitor C1 by a 2nd current source I2 and reaches a same level as the emitter potential of the TR 1 after the time t1, and reaches a level lower than the potential of the terminal 2 by VBE after a time t2, the TR 2 is turned on and the discharge of the capacitor C1 is finished. The operation of the TRs 1, 2 is inverted at the time T2. When an emitter waveform of the TRs 1, 2 is inputted to a limiter amplifier 3, a waveform delayed from the input signal by the time t1 is obtained from output terminals 4, 5.
申请公布号 JPH0411409(A) 申请公布日期 1992.01.16
申请号 JP19900114074 申请日期 1990.04.28
申请人 SANYO ELECTRIC CO LTD 发明人 EGAMI TAKESHI
分类号 H03K5/13;H03L7/08 主分类号 H03K5/13
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