| 摘要 |
Disclosed herein is a flash type EEPROM which includes a first memory cell array having a plurality of first memory cells, a second memory array having a plurality of memory cells which are smaller in number than the first memory cells, a voltage generator operatively generating an erasing voltage in an erase operation mode, a first transfer gate circuit operatively transferring the erasing voltage to each of the first and a second transfer gate circuit operatively transferring the erasing voltage to each of the second memory cells, the first transfer gate circuit having a current driving capability larger than the current driving capability of the second transfer gate circuit. <IMAGE> |
