| 摘要 |
A processor-based device (102) incorporating an on-chip trace cache (200) and supporting circuitry for providing software performance profiling information. A trigger control register (219a) is configured to initialize and trigger (start) a first on-chip counter upon entry into a selected procedure. A second trigger control register (219b) is used to stop the first counter when the procedure prologue of the selected procedure is entered. Counter values reflecting the lapsed execution time of the selected procedure are then stored in the on-chip trace cache. A second counter is also provided. The second counter runs continually, but is reset to zero following a stop trigger event caused by the second trigger control register. The stop trigger event also causes the value of the second counter to be placed in the on-chip trace cache (200). This second counter value provides the frequency of occurence of a procedure of interest, whereas the first counter provides information about the procedure's execution time. Either post-processing software executing on a target system, a host system utilizing a debug port, or off-chip trace capture hardware can be used to analyze the profile data.
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