发明名称 |
MULTICLOCK PARALLEL PROCESSOR |
摘要 |
<p>PROBLEM TO BE SOLVED: To provide a multiclock parallel processor for reducing the processing time and power consumption by operating respective reconfigurable integrated circuits at the optimum clock frequency corresponding to writable or rewritable circuit configuration information. SOLUTION: This device is provided with a storage means 36 storing the optimum clock frequency for operation corresponding to the circuit configuration information, an instruction control means 37 for extracting the circuit configuration information from the storage means 36 corresponding to the designation from the outside such as user, rewriting designated reconfigurable integrated circuits 32-35 and outputting the optimum clock frequency for operation corresponding to these reconfigurable integrated circuits as a control signal, and clock generating means 39 for operation for changing the rewritten reconfigurable integrated circuits into optimum clock frequency for operation corresponding to that control signal.</p> |
申请公布号 |
JP2000181566(A) |
申请公布日期 |
2000.06.30 |
申请号 |
JP19980355025 |
申请日期 |
1998.12.14 |
申请人 |
MITSUBISHI ELECTRIC CORP;MITSUBISHI ELECTRIC ENGINEERING CO LTD |
发明人 |
ASAMI HIROYOSHI;SATO HIROYUKI;IIDA MASAHIRO;MORI HAKURO |
分类号 |
G06F15/177;G06F1/04;G06F1/10;(IPC1-7):G06F1/04 |
主分类号 |
G06F15/177 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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