发明名称 DIGITAL IMAGE PROCESSOR
摘要 <p>PROBLEM TO BE SOLVED: To inhibit the ineffective processes against the use of an LSI chip which has limitation of the numbers of lines and pixels of an image in both image compression and expansion modes by recognizing the numbers of vertical lines and horizontal pixels of a current image, executing the compressing and expanding processes of the image in an effective range and inhibiting the compressing and expanding processes of the image in an ineffective range respectively. SOLUTION: If a compressing/expanding process instruction signal 11 received from a CPU 8 is kept within a process effective range that is decided by the vertical and horizontal synchronizing signals 9 and 10 which are received from a synchronizing production circuit 7, an image compressing/expanding LSI 4 compresses an input image 2 to output it as the output compression data 5 or expands the input compression data into an output image 3. At the same time, the CPU 8 outputs the signal 11 to the LSI 4 only when the vertical and horizontal counter value (line value and pixel value) 12 and 13 sent from the circuit 7 are kept within a process effective range of the LSI 4. It is not required to output the signal 11 as long as the value 12 and 13 are kept in a process ineffective range, and the image data are directly outputted with no compression nor expansion.</p>
申请公布号 JP2000184372(A) 申请公布日期 2000.06.30
申请号 JP19980353697 申请日期 1998.12.14
申请人 HITACHI DENSHI LTD 发明人 SATO MASASHI
分类号 H04N19/102;H04N7/24;H04N19/00;H04N19/134;H04N19/196;(IPC1-7):H04N7/24 主分类号 H04N19/102
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