DELAY LOCKED LOOP FOR TIMING RECOVERY AND WRITE PRECOMPENSATION FOR A READ CHANNEL OF A MASS DATA STORAGE DEVICE, OR THE LIKE

摘要

An integrated delay locked loop circuit (10) and method are presented. The circuit (10') includes a source of multiple clock signals (24), each of different relative phase. A plurality of clock selection multiplexers (30-33) are connected to receive the multiple clock signals (16). A control circuit (66) is connected to control each of the plurality of clock selection multiplexers (30-33) to pass a respective selected one of the multiple clock signals (16) to a clock selection output (43-46). If one of the clock selection multiplexers (30-33) is selected to pass a particular one of the clock signals (16) to its clock selection output (43-46), the other clock selection multiplexers are prevented from passing the particular one of the clock signals to their respective clock selection outputs. A plurality of output multiplexers (60-63) are connected to receive outputs from he clock selection multiplexers (30-33). Each of the output multiplexers (60-63) is controlled by the control circuit (66) to select which of the clock selection multiplexer outputs (43-46) is passed to its output.