| 摘要 |
There is provided a semiconductor integrated circuit in which a source clock (S 101 ) is inputted to a delay circuit ( 3 ), a counter circuit ( 6 ) is operated in response to a delay clock (S 102 ) which is the output of the delay circuit ( 3 ), a clock used as a system clock by an internal circuit ( 4 ) is selected from the source clock (S 101 ) and the delay clock (S 102 ) based on the value of the counter circuit ( 6 ), and the duty cycle of the system clock is changed, so that it is possible to reduce electromagnetic interference resulting from harmonics generated by the switching of the internal circuit.
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