发明名称 |
LOW-POWER RETENTION FLIP-FLOPS |
摘要 |
A retention flip-flop is provided. The flip-flop includes a clock generation circuit, a master latch circuit, and a salve latch circuit. The clock generation circuit generates first and second clock signals at a first mode. The master latch circuit performs a first latch operation on an input signal from the input terminal according to the first and second clock signals to generate a first latched signal at a first node at the first mode. The salve latch circuit performs a second latch operation on the first latched signal according to the first and second clock signals to generate a second latched signal at a second node at the first mode. At a sleep or power-down mode, the total number of transistors in the clock generation circuit and the salve latch circuit is equal to or less than eight. |
申请公布号 |
US2016211831(A1) |
申请公布日期 |
2016.07.21 |
申请号 |
US201514922405 |
申请日期 |
2015.10.26 |
申请人 |
MediaTek Inc. |
发明人 |
HUANG Rei-Fu |
分类号 |
H03K3/012;H03K3/3562;H03K3/037 |
主分类号 |
H03K3/012 |
代理机构 |
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代理人 |
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主权项 |
1. A flip-flop having an input terminal and an output terminal, comprising:
a clock generation circuit to generate a first clock signal and a second clock signal inverse to the first clock signal when the flip-flop is at a first mode; a master latch circuit to perform a first latch operation on an input signal from the input terminal according to the first clock signal and the second clock signal to generate a first latched signal at a first node when the flip-flop is at the first mode; and a salve latch circuit, coupled to the first node, to perform a second latch operation on the first latched signal according to the first clock signal and the second clock signal to generate a second latched signal at a second node when the flip-flop is at the first mode, wherein the second latched signal is coupled to the output terminal of the flip-flop, and the salve latch circuit comprises:
a first inverter having an input terminal coupled to the first node and an output terminal coupled to the second node;a first pass gate coupled between the second node and a third node;a second inverter having an input terminal coupled to the third node and an output terminal coupled to the input terminal of the first inverter. |
地址 |
Hsin-Chu TW |