发明名称 SiCエピタキシャルウェハ及びその製造方法
摘要 Provided are a SiC epitaxial wafer in which the surface density of stacking faults is reduced, and a manufacturing method thereof. The method for manufacturing such a SiC epitaxial wafer comprises a step of determining a ratio of basal plane dislocations (BPD), which causes stacking faults in a SiC epitaxial film of a prescribed thickness which is formed on a SiC single crystal substrate having an off angle, to basal plane dislocations which are present on a growth surface of the SiC single crystal substrate, a step of determining an upper limit of surface density of basal plane dislocations on the growth surface of a SiC single crystal substrate used based on the above ratio, and a step of preparing a SiC single crystal substrate which has surface density equal to or less than the above upper limit, and forming a SiC epitaxial film on the SiC single crystal substrate under the same conditions as the growth conditions of the epitaxial film used in the step of determining the ratio.
申请公布号 JP5961357(B2) 申请公布日期 2016.08.02
申请号 JP20110197626 申请日期 2011.09.09
申请人 昭和電工株式会社 发明人 百瀬 賢治;小田原 道哉;武藤 大祐;影島 慶明
分类号 H01L21/205;C23C16/42;C30B25/20;C30B29/36 主分类号 H01L21/205
代理机构 代理人
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