| 摘要 |
PROBLEM TO BE SOLVED: To provide a verification device, a method, and a program that can efficiently reduce the time for verification of a semiconductor integrated circuit.SOLUTION: The verification device according to the present invention generates a net list of a non-synchronous circuit from a net list of a semiconductor integrated circuit to be verified, and executes a gate-level simulation on a non-synchronous circuit indicated by the non-synchronous net list. The verification device extracts an input value and an output value of a register of the semiconductor integrated circuit and non-synchronous pass information, from the RTL descriptions of the semiconductor integrated circuit to be verified, and extracts an input value and an output value of the pass indicated by the non-synchronous pass information. The verification device executes a gate-level simulation based on an input value and an output value of the pass indicated by the non-synchronous pass information.SELECTED DRAWING: Figure 1 |
