| 摘要 |
<p>PROBLEM TO BE SOLVED: To reduce electric power consumption during a sleep, and to secure a long sleep time. SOLUTION: This system is constituted of an oscillation source clock generating means 10 for generating an oscillation source clock 101, a frequency divider 20 for dividing the oscillation source clock 101, a sleep control circuit 30 for switching a sleep signal 102 to an active/nonactive one in response to a sleep control signal 107 input from a sleep control signal input terminal 70, a clock switching circuit 40 for switching a clock by the sleep signal 102 output from the sleep control circuit 30, a frequency multiplying circuit 50 for multiplying and dividing a clock 103 output from the clock switching circuit 40, and a clock interrupting circuit 60 for a clock 104 output from the frequency mutiplying circuit 50 by a period during the sleep signal 102 is active.</p> |
