发明名称 |
Reliable packaging and interconnect structures |
摘要 |
Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a top surface and portions of the side walls of the interconnect structure covered in a dissimilar material. In some embodiments, the dissimilar material can be a conductive material or a nano-alloy. The interconnect structure can be formed by removing a portion of the interconnect structure, and covering the interconnect structure with the dissimilar material. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure. |
申请公布号 |
US9385036(B2) |
申请公布日期 |
2016.07.05 |
申请号 |
US201414329744 |
申请日期 |
2014.07.11 |
申请人 |
Invensas Corporation |
发明人 |
Uzoh Cyprian Emeka;Haba Belgacem;Mitchell Craig |
分类号 |
H01L21/78;H01L21/768;H01L23/48;H01L23/522;H01L23/532;H01L23/528;H01L23/00 |
主分类号 |
H01L21/78 |
代理机构 |
Haynes and Boone, LLP |
代理人 |
Haynes and Boone, LLP |
主权项 |
1. A method of manufacturing a structure comprising a semiconductor device, the method comprising:
forming a first opening in a substrate, the first opening extending down into the substrate; forming a first feature for an interconnect structure, the first feature being electrically conductive and having a sidewall in the first opening; and forming a second feature overlying the first feature and extending down into the first opening along the sidewall of the first feature, the second feature comprising a first material different from any material in the sidewall and top of the first feature. |
地址 |
San Jose CA US |