发明名称 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
摘要 A method for manufacturing a semiconductor device includes forming a fin structure over a substrate. An isolation insulating layer is formed so that an upper part of the fin structure protrudes from the isolation insulating layer. A gate structure is formed over a part of the fin structure. Recesses are formed in the isolation insulating layer at both sides of the fin structure. A recess is formed in a portion of the fin structure which is not covered by the gate structure. The recess in the fin structure and the recesses in the isolation insulating layer are formed such that a depth D1 of the recess in the fin structure and a depth D2 of the recesses in the isolation insulating layer measured from an uppermost surface of the isolation insulating layer satisfy 0≦D1≦D2 (but D1 and D2 are not zero at the same time).
申请公布号 US2016211372(A1) 申请公布日期 2016.07.21
申请号 US201514749597 申请日期 2015.06.24
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD 发明人 YU Cheng-Yen;CHANG Che-Cheng;CHENG Tung-Wen;Zhang Zhe-Hao;YOUNG Bo-Feng
分类号 H01L29/78;H01L29/66;H01L29/16;H01L29/267;H01L21/02;H01L27/088;H01L29/08;H01L29/06;H01L21/8234;H01L29/165 主分类号 H01L29/78
代理机构 代理人
主权项 1. A method for manufacturing a semiconductor device, comprising: forming a fin structure over a substrate; forming an isolation insulating layer so that an upper part of the fin structure protrudes from the isolation insulating layer; forming a gate structure over a part of the fin structure and over the isolation insulating layer; forming recesses in the isolation insulating layer at both sides of the fin structure; and forming a recess in a portion of the fin structure which is not covered by the gate structure, wherein the recess in the fin structure and the recesses in the isolation insulating layer are formed such that a depth D1 of the recess in the fin structure and a depth D2 of the recesses in the isolation insulating layer measured from an uppermost surface of the isolation insulating layer satisfy 0≦D1≦D2, where D1 and D2 are not zero at the same time.
地址 Hsinchu TW