| 摘要 |
PURPOSE:To easily execute fault analysis and to shorten the time to be required for fault analysis. CONSTITUTION:In a fault analyzing system for a microcomputer(MC) system consisting of a CPU 1 and a built-in RAM 2 as basic constitution, an interruption is generated from a watch-dog timer(WDT) at the abnormal operation of the MC system, and in the case of restoring the MC system, the interruption generating state is latched by an FF circuit 8, a write-only RAM 7 for writing the same contents as the RAM 2 is turned to a write inhibiting state in accordance with the latched state of the FF circuit 8, the contents of the RAM 2 at the time of generating abnormal operation are stored in a write-only RAM (attachable/detachable) 7, and the contents of the RAM 7 are read out by an ICE or the like to execute fault analysis. |
