| 摘要 |
An ATM switch having a plurality of input-ports and a plurality of output ports allowing a plurality of priority levels, which is highly modular allowing expansion of the number of cell buffers in a shared buffer pool, thus efficiently handling bursty traffic of one-to-one and one-to-many destination ports, using the bit slicing concept to reduce the operating speed of the switch, and decrease the cell buffer size requirement per slice along with reducing the number of shared queue memories per slice, aiding cost effective and efficient, very large scale integration (VLSI) implementation. It also allows configurability of input link speeds, taking care of the order of cell delivery to the output ports. The switch on receiving the input cell, searches for a free buffer in the shared pool, then routes the cell into this buffer and indexes the pointer into an output queue called the queue management module which uses a shared pool of queue memories. The buffers are then read out in the order of priority and sequence of arrival at the input, by this queue management module. It provides initialization, control and status monitoring features too, through a processor interface module.
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