| 摘要 |
<p>Disclosed is a timing delay circuit for use in a high-speed memory (SRAM, DRAM) array, for timing of a differential sense amplifier (78). A timing chain (1, 11, 31-33, 67, 68) is used to generate the required set sense amplifier (SSA) delay from the leading edge of the ram input clock (82). The delay varies, depending on CMOS process parameters and applied conditions, such as supply voltage and temperature. It is therefore suggested to introduce a voltage dependent current sink/source (61) in the timing chain for the SSA signal which counteracts the delay reduction which is obtained when the supply voltage is raised. The signal drop of the SSA signal due to activation of the current sink/source leads to an additional delay of the SSA signal.</p> |
