发明名称 Fabrication process for a connection between multilayer wirings in a semiconductor device
摘要 <p>An interlayer insulation layer (20) is formed on a semiconductor substrate (1) and a groove of a wiring shape is formed in the interlayer insulation layer (20). Then, the groove is buried with conductor. A part of the conductor is covered with a mask material, and a part of the conductor not covered with the mask is etched to form a recess. Thus, a first wiring (25) is defined at a part of the conductor under the recess, and a columnar projection (26) to be a connecting portion of wirings is defined at a side of the recess on the first wiring (25). An insulation layer (28) is buried in the recess except for the upper surface of the columnar projection (26). A second wiring (30) covering at least a part of the exposed upper surface of the columnar projection (26) is formed. &lt;IMAGE&gt;</p>
申请公布号 EP0810651(A2) 申请公布日期 1997.12.03
申请号 EP19970108640 申请日期 1997.05.28
申请人 NEC CORPORATION 发明人 ITO, SHINYA
分类号 H01L21/768;H01L21/3205;H01L23/52;H01L23/522;(IPC1-7):H01L21/768 主分类号 H01L21/768
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