发明名称 |
Voltage generator circuit and method for controlling thereof |
摘要 |
A voltage generator circuit which is capable of preventing the generation of a through current in a transition to a power-down mode to reduce current consumption. The voltage generator circuit includes a voltage generator activated by a reference voltage to generate an output voltage. A reference voltage clamp circuit is coupled to the voltage generator for clamping the reference voltage to a first voltage in response to a power-down signal to deactivate the voltage generator. An output voltage clamp circuit is coupled to the voltage generator for clamping the output voltage to a second voltage. A control circuit is coupled to the output voltage clamp circuit for enabling the output voltage clamp circuit after the voltage generator is deactivated in response to the power-down signal.
|
申请公布号 |
US2002167350(A1) |
申请公布日期 |
2002.11.14 |
申请号 |
US20020061183 |
申请日期 |
2002.02.04 |
申请人 |
FUJITSU LIMITED |
发明人 |
SATO HAJIME;SAITO SYUICHI;IWASE AKIHIRO |
分类号 |
G11C5/14;G05F1/46;(IPC1-7):G05F1/10 |
主分类号 |
G11C5/14 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|