| 摘要 |
PROBLEM TO BE SOLVED: To expand the field of application of a scan test by a scan test circuit from a conventional static logic failure detection up to a timing failure detection at an actual operating frequency. SOLUTION: The scan test circuit is constituted in such a way that the output of a flip-flop FF1 connected to a logic circuit X1 is connected to the input of a flip-flop FF3 connected to a logic circuit X2, that the output of the flip-flop FF3 is connected to the input of a flip-flop FF2 connected to the logic circuit X1, and that the output of the flip-flop FF2 is connected to the input of a flip-flop FF4 connected to the logic circuit X2. An input value is given to the same logic circuit, and a plurality of lip-flops which are scan-chain- connected are arranged so as not to be adjacent on a scan chain. |
