| 摘要 |
<p>A CPU (10) having an SMT function of executing a plurality of threads composed of a series of instructions expressing a processing comprises a decoding section (109) for decoding a processing expressed by the instructions of the threads, an instruction buffer (104) for acquiring the instructions from the threads and holding them and inputting the held instructions to the decoding section (109) in the order in the threads, and an execution pipeline (220) for executing the processing of the instructions decoded by the decoding section (109). The decoding section (109) confirms whether or not conditions that the instructions can be executed are in order at the time of the decoding of the instructions and requests the re-input of an instruction held in the instruction buffer (104) subsequent to an instruction whose conditions are not in order to the decoding section (109).</p> |
