Adder circuit using decimal counter code

摘要

The adder circuit according to the subject of the invention differs from the adder circuit according to the main Patent Application (P 3834202.2) mainly in that it can process only summands which are in decimal counter code, and that the result number is in decimal counter code. The conversion of the summands is more difficult than in the adder circuit according to P 3834202.2, and takes place in the input circuits 3a and 3b. The output circuit consists of circuits 6 to 8. The number 7 is represented by the potential series LLHHHHHHH. <IMAGE>