| 摘要 |
<p>PURPOSE:To allow the detection of faults of all memory cells without depending on the data built into the memory cells. CONSTITUTION:Transistors 6 which maintain all bit lines 5 at an H level and transistors 7 which maintain all the bit lines 5 at an L level are provided separately from an ordinary reading out state. The operations in which the three states; the 1st state of the H level, the 2nd state of the L level and the test state to execute ordinary reading out constitute one cycle in order of the 1st state, the test state, the 2nd state, and the test state are executed with all addresses. The respective bit line signals always invert in logic level at either of the time of the transfer from the 1st state to the test state or the time of the transfer from the 2nd state to the test state and, therefore, such a fault that the memory cells are fixed at the off state and fail to attain the on state and such a fault that the memory cells are disconnected from the bit lines are detected.</p> |
