发明名称 CONTACT MATCHING FOR NONVOLATILE MEMORY DEVICE
摘要 PURPOSE: To provide a proper technique for a bit line contact that is self-aligned partially regarding a layout and a manufacturing technique for an EPROM or a similar device, and further a self-aligned burial Vss line and hence bring it into contact with a substrate over its total length and reduce its dimension. CONSTITUTION: A conductive structure 12 is constituted on a lower structure 10, an opening 14 is provided between them, and a contact to the structure 10 is separated from the conductive structure 12. Well known depositon, etching, and etchback processes are used. The film thickness of an oxide deposition layer is changed relatively and a self-alignment process is used to form the contact and a burial Vss , thus facilitating the formation.
申请公布号 JPH0685277(A) 申请公布日期 1994.03.25
申请号 JP19920222966 申请日期 1992.08.21
申请人 ESU JII ESU TOMUSON MAIKUROEREKUTORONIKUSU INC 发明人 FURANKU AARU BURAIANTO;TSUIU SHII CHIYAN
分类号 G11C17/00;H01L21/768;H01L21/8247;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):H01L29/788;G11C16/02 主分类号 G11C17/00
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