| 摘要 |
PURPOSE: To prevent skew from being generated among plural clock signals by outputting the respective operation clock signals completely periodic with the phase of a reference clock while ANDing them with a clock synthesizing means by using a timing signal generating means. CONSTITUTION: A reference clock generating means 7 generates a reference clock REFCLK 1 and simultaneously inputs it through a distributing circuit 9 for REFCLK 1 to respective clock synthesizing means 10-1 to 10-n. These respective means 10-1 to 10-n AND the reference clock REFCLK 1 inputted through the circuit 9 and timing signals T11 , T21 , and Tnt inputted from timing signal distributing circuits 9-1 to 9-n and output operation clock signals CLK-1 to CLK-n to respectively correspondent clock operating circuits 11-1 to 1-n. As a result, the respective operation clock signals CLK-1 to LK-n completely synchronized with the phase of the reference clock REFCLK 1 can be outputted and the skew can be prevented from being generated among the clock signals. |
