发明名称 VECTOR PROCESSOR
摘要 PROBLEM TO BE SOLVED: To improve a list vector instruction performance without increasing a hardware quantity by providing a memory access control part with a congestion mediation circuit, m-pieces of vector element selection circuits and an output buffer which simultaneously stores maximum m-pieces of vector elements. SOLUTION: Input registers 121a-121d receive the load/storage requests of a list vector from a vector operation part 110. Input buffers 122a-122d are buffers for requests which are continuously issued. An even port arbiter 128a and an odd port arbiter 128b are output port contention mediation circuits with only the even/odd elements of input ports as objects. Even port cross bars 124 and odd port cross bars 125 transfer only the vector elements of the even/odd input ports to output ports. Output buffers 126a-126d simultaneously store the two vector elements to the maximum and store them so that an order for outputting the vector element from the even port cross bars 124 always becomes first.
申请公布号 JPH11232078(A) 申请公布日期 1999.08.27
申请号 JP19980031177 申请日期 1998.02.13
申请人 NEC KOFU LTD 发明人 IGAWA YASUHIRO
分类号 G06F7/00;G06F15/167;G06F17/16 主分类号 G06F7/00
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