发明名称 PLD SYSTEM
摘要 PROBLEM TO BE SOLVED: To provide PLD(programmable logic device) system where a PLD is surely initialized at application of power. SOLUTION: The PLD 1 is an aggregate of logic circuits where optional circuit functions can be realized. A power supply applies a voltage V1 to the PLD 1. A delay pulse circuit 3 gives an initializing signal V2 to a CONFIC terminal of the PLD 1 when a prescribed time elapses after the voltage V1 from the power supply 4 rises and the voltage V1 is settled. Every time a memory 2 receives a clock C from the PLD 1, the memory 2 gives serial data D to set a circuit function and the PLD 1 uses the data D and completes initializing.
申请公布号 JP2000183728(A) 申请公布日期 2000.06.30
申请号 JP19980359491 申请日期 1998.12.17
申请人 NEC MIYAGI LTD 发明人 SATO TAKASHI
分类号 H03K19/173;(IPC1-7):H03K19/173 主分类号 H03K19/173
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