METHOD AND APPARATUS FOR ADJUSTING THE PHASE OF INPUT/OUTPUT CIRCUITRY

摘要

Input/output clockphase adjustment circuitry for use with input/output circuitry of an integrated circuit chip. In one embodiment, an integrated circuit chip includes a phase adjustment circuit coupled to receive a system clock. The phase adjustment circuit generates an input/output clock coupled to be received by an input/output circuit of an integrated circuit chip for input/output data transfers in a system. The phase adjustment circuit includes a phase locked loop circuit coupled to receive the system clock through a first delay circuit. The input/output clock generated by the phase locked loop circuit is received through a second delay circuit at a feedback clock input of the phase locked loop circuit. The first and second delay circuits are used to control the phase of the input/output clock generated by the phase locked loo circuit relative to the system clock. In one embodiment, a third delay circuit is included in an input/output data path of the input/output circuit of the integrated circuit. The third delay circuit enables input and output data transmission from the integrated circuit to be clocked out of phase with the system clock.