发明名称 System and Method for Circuit Symbolic Timing Analysis of Circuit Designs
摘要 A method, data processing system, and computer program product are provided for performing time-based symbolic simulation. A delay-aware representation of a circuit is created that includes a plurality of circuit nodes. The data-aware representation is simulated. In particular, the simulator simulates transitions from a first set of circuit nodes to a second set of circuit nodes selected from the plurality of circuit nodes, the simulating based on executing a first set of simulation events. A second set of simulation events is then generated in response to executing the first set of simulation events. During the simulation, a time is computed for each of the transitions. An an event scheduling diagram is constructed during simulation. The event scheduling diagram depicts the transitions and the times of the transitions.
申请公布号 US2008071515(A1) 申请公布日期 2008.03.20
申请号 US20060532268 申请日期 2006.09.15
申请人 BHADRA JAYANTA;ABADIR MAGDY S;GAO PING;MCDOUGALL TIMOTHY DAVID 发明人 BHADRA JAYANTA;ABADIR MAGDY S.;GAO PING;MCDOUGALL TIMOTHY DAVID
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项
地址