| 摘要 |
Logic circuit comprising-at least a first combinational logic circuit 42-a first data latch 44 having a data input d and a data output q, said data output q being connected to an input of said first combinational logic circuit 42,-a second scannable data latch 43 having an output q connected to the data input d of said first data latch 44 and-a third scannable data latch 47 having an input d connected to an output of said first combinational logic circuit 42, wherein the second scannable data latch 43 is adapted to being driven by a first clock clk1, the first data latch 44 and the third scannable data latch 47 are adapted to being driven by a second clock clk2, the first and second clocks clk1 and clk2 being non-overlapping clock signals.
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