发明名称 |
Apparatus and method for multiphase SMPS interleaving |
摘要 |
In described examples, a phase interleaver obtains (i) a first signal indicating a variance between a reference voltage and a regulated output voltage and (ii) a second signal indicating a voltage across an energy storage device. A voltage regulator includes multiple phase blocks collectively configured to generate the regulated output voltage. In a repeating cycle, (i) the voltage across the energy storage device is increased while the second signal is less than the first signal and (ii) in response to a determination that the second signal is greater than the first signal, the energy storage device is substantially discharged, multiple stages of a clock divider are transitioned in the phase interleaver, and a set of control signals is output from the clock divider. The control signals have a common switching frequency and a common switching period. The control signals control the phase blocks active in generating the output voltage. |
申请公布号 |
US9383761(B2) |
申请公布日期 |
2016.07.05 |
申请号 |
US201414323870 |
申请日期 |
2014.07.03 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
Mercer Steven Mark |
分类号 |
G05F1/575;H02M3/158 |
主分类号 |
G05F1/575 |
代理机构 |
|
代理人 |
Davis, Jr. Michael A.;Cimino Frank D. |
主权项 |
1. A method comprising:
obtaining at a phase interleaver (i) a first signal indicating a variance between a reference voltage and a regulated output voltage and (ii) a second signal indicating a voltage across an energy storage device, wherein a voltage regulator includes multiple phase blocks collectively configured to generate the regulated output voltage; and in a repeating cycle:
while the second signal is less than the first signal, increasing the voltage across the energy storage device; andin response to a determination that the second signal is greater than the first signal, substantially discharging the energy storage device, transitioning multiple stages of a clock divider in the phase interleaver, and outputting a set of control signals from the clock divider, the set of control signals having a common switching frequency and a common switching period; wherein the set of control signals controls the phase blocks in the voltage regulator that are active in generating the regulated output voltage. |
地址 |
Dallas TX US |